As a package for accommodating a semiconductor device, there is known a construction comprising a substrate for placement of a semiconductor device, and an input-output terminal for providing electrical connection between the semiconductor device and an external electric circuit board (refer to Japanese Unexamined Patent Publication JP-A 2003-218258 and Japanese Unexamined Patent Publication JP-A 2010-199277, for example). In such a package, a plurality of metallization wiring layers are formed on the upper surface of the input-output terminal. Each of the metallization wiring layers is connected with a lead terminal for providing electrical connection between the metallization wiring layer and an external electric circuit board.
In recent years, downsizing has come to be demanded of packages. Moreover, as packages become more and more sophisticated, the number of lead terminals to be connected to an input-output terminal is on the increase. In a downsized package, or in the case of increasing the number of lead terminals to be connected to an input-output terminal, the spacing between adjacent lead terminals will be narrowed, which may pose the risk of electrical short-circuiting between the lead terminals.
An object of the invention is to provide a semiconductor device housing package that requires no lead terminal.